Project and development of hardware accelerators for fast computing in multimedia processing

2017 - 2018The main aim of the present research work is to project and develop very large scale electronic integrated circuits, with particular attention to the ones devoted to image processing applications and the related topics. In particular, the candidate has mainly investigated four topics, detailed in the following. First, the candidate has developed a novel multiplier circuit capable of obtaining floating point (FP32) results, given as inputs an integer value from a fixed integer range and a set of fixed point (FI) values. The result has been accomplished exploiting a series of theorems and results on a number theory problem, known as Bachet’s problem, which allows the development of a new Distributed Arithmetic (DA) based on 3’s partitions. This kind of application results very fit for filtering applications working on an integer fixed input range, such in image processing applications, in which the pixels are coded on 8 bits per channel. In fact, in these applications the main problem is related to the high area and power consumption due to the presence of many Multiply and Accumulate (MAC) units, also compromising real-time requirements due to the complexity of FP32 operations. For these reasons, FI implementations are usually preferred, at the cost of lower accuracies. The results for the single multiplier and for a filter of dimensions 3x3 show respectively delay of 2.456 ns and 4.7 ns on FPGA platform and 2.18 ns and 4.426 ns on 90nm std_cell TSMC 90 nm implementation. Comparisons with state-of-the-art FP32 multipliers show a speed increase of up to 94.7% and an area reduction of 69.3% on FPGA platform. ... [edited by Author]XXXI cicl

Characterization of SiGe layers grown by Trisilane and Germane at low temperatures for BiCMOS application

Low temperature epitaxy (LTE) of SiGe by chemical vapor deposition (CVD) has attracted dramatic attention during the last decade for CMOS and BiCMOS application. LTE relates to a temperature range of 350÷650 °C. The low temperature budget provides the possibility of integrating epitaxy in the process line when the sensitive active parts are already present on the chips. In this case, the benefits of LTE are to avoid the thermal mismatch between different layers in the transistors, preventing damages to the poly gate and to ensure the integrity of thin gate oxide. The challenge to deal with the lowering temperature process is the quality of epitaxial layer. In particular, the low temperature processing results in low growth rates and more oxygen (or water moisture) contamination in the layer growth. For these reasons, particular attention has been paid to islands formation at the interface and within the layer. Choosing appropriate Si precursor, optimizing the growth parameters and reducing oxygen (or moisture) contamination are critical issues for growing high quality epitaxial layers at low temperatures. This thesis work presents the characterization of layers grown using Trisilane (Si3H8), Germane (GeH4) and Hydrochloric acid (HCl) as precursor gases at LTE. Characterization tools were high-resolution scanning electron microscope (HRSEM), Secondary ion mass spectroscopy (SIMS), high-resolution x-ray diffraction (HRXRD) and noise measurements. The results of this work suggest that only electrical measurements are most sensitive way to study the effects of low amounts of contamination on crystal quality of LTE grown structures. It also shows that the presence of HCl in the chamber increases the noise level in these types of structures. This higher level of noise is believed to be a result of higher defect density due to the etching caused by HCl and metal contamination that could arise from the aging and the corrosion of the pipelines

FPGA optimization of convolution-based 2D filtering processor for image processing

The Bachet weight decomposition method is used to design a new 2D convolution-based filter, specifically aimed to image processing. The filter substitutes multipliers with simplified floating point adders to emulate standard 32 bit floating point multipliers, by using a set of pre-computed coefficients. A careful organization of the memory, together with the optimized distribution of the related hard macros in the FPGA fabric, allow the elaboration of the data in raster scan order, as those directly provided by an acquisition source, without the need of frame buffers or additional aligning circuitry. The proposed design achieves a state-of-the-art critical path delay of 4.7 ns on a Xilinx Virtex 7 FPGA

Application specific image processor for the extension of the dynamic range of images with multiple resolutions

A new processor is proposed, capable to expand the dynamic range of input images in real-time. With respect to the existent literature, the processor presents the unique feature of elaborating images at different resolutions, up to 4K UHDTV, by deriving a specific algorithm from the most effective methods presented in the literature. Additionally, the proposed design is capable to elaborate the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor exhibits a latency of 32.4ms (31 fps), while a 4K frame requires 129ms (8 fps) to be processed

Design and FPGA implementation of a real-time processor for the HDR conversion of images and videos

In this paper a multiresolution architecture to expand the dynamic range of low dynamic range (LDR) images to 32-bit high dynamic range (HDR) counterpart is presented. The processor is capable to provide on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to images images up to full-HD images (1920×1080 pixels) using 25×9 filtering and up to 4K UHDTV images (3840×2160 pixels) using 25×5 filtering without frame buffers. To this end, a "hardware friendly" algorithm has been derived from the most effective methods presented in the literature. Additionally, the proposed design is capable of processing the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor achieves state-of-the art performances

Hardware architecture for 2D Gaussian filtering of HD images on resource constrained platforms

A bi-dimensional filter for high accuracy image processing is implemented by using a novel partitioning method. The method is based on a number theory theorem, which permits to reduce the complexity of the operation to that of an adder chain and also the amount of the coefficients stored in memory, improving the memory organization. To show the advantage of such method, we implemented a Floating Point 32 (FP32) in hardware filtering applications and, in particular, for 2D FIR filters. Using Xilinx Virtex 7 Field Programmable Gate Array (FPGA) we obtain a critical path delay of 4.7ns which is comparable with the state-of-Art

Hardware accelerator using Gabor filters for image recognition applications

This paper presents the design of a new hardware accelerator, filtering the input data using Gabor functions and dedicated to image processing. The proposed design obtains a great reduction in terms of resources if compared to other state-of-The-Art implementations. This is done exploiting the separability of Gabor filters along certain orientations and through a reorganization of the arithmetic units and the memory structures, achieved thanks to the absence of frame buffers to store the entire input image and partially processed data. All the above reported features allow the design to obtain real-Time performances. The design has been targeted to a Xilinx Virtex 7 ASIC board and to CMOS 90nm std-cells, obtaining a minimum operating clock period of 5.8 ns for the FPGA implementation and of 2.9 ns for the std-cell one. The above reported results allow to process 83 and 168 1920Ã\u971080 pixels (Full-HD) frame-per-second, respectively

Design of a Gabor Filter HW Accelerator for Applications in Medical Imaging

The Gabor filter (GF) has been proved to show good spatial frequency and position selectivity, which makes it a very suitable solution for visual search, object recognition, and, in general, multimedia processing applications. GFs prove useful also in the processing of medical imaging to improve part of the several filtering operations for their enhancement, denoising, and mitigation of artifact issues. However, the good performances of GFs are compensated by a hardware complexity that traduces in a large amount of mapped physical resources. This paper presents three different designs of a GF, showing different tradeoffs between accuracy, area, power, and timing. From the comparative study, it is possible to highlight the strength points of each one and choose the best design. The designs have been targeted to a Xilinx field-programmable gate array (FPGA) platform and synthesized to 90-nm CMOS standard cells. FPGA implementations achieve a maximum operating frequency among the different designs of 179 MHz, while 350 MHz is obtained from CMOS synthesis. Therefore, 86 and 168 full-HD (1920 × 1080) f/s could be processed, with FPGA and std-cell implementations, respectively. In order to meet space constraints, several considerations are proposed to achieve an optimization in terms of power consumption, while still ensuring real-time performances